In recent years, for satisfying demands for high-speed semiconductor devices, semiconductor devices such as high-speed MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) in which a Si layer obtained by performing epitaxial growth through a SiGe (Silicon Germanium) layer on a Si (Silicon) substrate is used for a channel region have been suggested.
In this case, because a SiGe crystal is larger in lattice constant than a Si crystal, tensile strain is generated in a Si layer epitaxially-grown on a SiGe layer (hereinafter, a Si layer in which strain is generated in this manner is referred to as a strained Si layer). Energy band structure of a Si crystal is changed by the strained stress, and as a result, degeneracy of the energy band is removed and high-energy band with high carrier mobility is formed. Therefore, the MOSFET that the strained Si layer is used as a channel region shows high-speed operation property that is about 1.3-8 times higher than usual.
Because magnitude of the tensile strain generated in the strained Si layer becomes larger along with Ge concentration of the SiGe layer being higher, the Ge concentration of the SiGe layer is an important parameter. Hereinafter, a SiGe layer having Ge composition rate X (0<X<1) is occasionally described as a Si1-XGeX layer.
As a method for forming such a strained Si layer, besides the above method that an epitaxial method is main, there is a known method for forming a Si1-XGeX layer on a silicon substrate to be a bond wafer, producing a bonded SOI substrate that a surface of the formed Si1-XGeX layer of the bond wafer is bonded to a silicon substrate to be a base wafer through an oxide film and thereby to be SOI (Silicon On Insulator) structure, and then thinning the silicon substrate of the bond wafer to be a strained Si layer, for example, as disclosed in Japanese Patent Application Laid-open (kokai) No. 2001-217430 and No. 2002-164520. In this case, as disclosed in Japanese Patent Application Laid-open (kokai) No. 2002-164520, it is also possible that a surface of the Si1-XGeX layer is subjected to thermal oxidation according to need thereby to be a condensation SiGe layer that the Ge concentration is enhanced.
In this case, the thinning of a silicon substrate of the bond wafer is performed with a grinding and polishing method, vapor etching such as PACE (Plasma Assisted Chemical Etching) method, an ion implantation delamination method (which is also referred to as a smart cut [a registered trademark] method), or the like.
The ion implantation delamination method is a technology of, implanting at least one of a hydrogen ion and rare gas ions from a surface of a bond wafer, namely, a surface of the Si1-XGeX layer, to form a micro bubble layer inside the bond wafer such as near the surface thereof, superposing closely the bond wafer in the ion implanted surface side on a base wafer through an oxide film, then performing heat treatment (delaminating heat treatment) to delaminate the bond wafer as a thin film so that the micro bubble layer is a cleavage plane (a delaminating plane), and further performing heat treatment (bonding heat treatment) to bond the two wafers tightly to provide a bonded wafer.
In the disclosure of Japanese Patent Application Laid-open (kokai) No. 2002-305293, it is disclosed that a separating layer is formed by ion implantation into a silicon substrate of a bond wafer in which a Si1-XGeX layer, a silicon layer, and an insulator layer are formed on the silicon substrate. And a surface of the insulator layer of the bond wafer is bonded to a base wafer. Then, a silicon layer of the delaminated layer that is delaminated at the separating layer and transferred to the base wafer side is made to be a strained Si layer.
In general, in a bonded substrate such as a bonded wafer, it is desired that bonding force of the bonded plane is strong enough to prevent generation of problems such as delamination at the bonded plane. In general, evaluation of the bonding force at the bonded plane of the bonded substrate can be performed by an evaluation of surface energy of the bonded plane which is proportional to the bonding force. Measurement of the surface energy can be performed by using a razor-blade insertion method as disclosed in Japanese Patent Application Laid-open (kokai) No. 7-29782.
In the case that a surface of a SiGe layer is bonded to another silicon substrate through an oxide film as disclosed in Japanese Patent Application Laid-open (kokai) No. 2001-217430, particles or contaminants on the surfaces need to be removed by cleaning the bonded plane before bonding is performed. In the cleaning step, so-called SC-1 cleaning in which a mixed aqueous solution of NH4OH and H2O2 (SC-1: Standard Cleaning 1) that is one of general cleaning liquids for a silicon substrate is used as a cleaning liquid is generally performed.